Monolithically integrated enhancement-mode InP MISFET inverter
作者： A. Antreasyan , P.A. Garbinski , V.D. Mattera , N.J. Shah , H. Temkin
DOI: 10.1049/EL:19860693
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摘要: Three InP MISFETs have been monolithically integrated on an Fe-doped semi-insulating substrate in conjunction with three load resistors forming inverter. The epitaxial layers grown by chloride vapour-phase epitaxy. exhibit transconductances as high 200 mS/mm for a gate length of 1 μm. circuit consists one MISFET that is operated transistor-inverter stage isolation and two-stage inverter whose output connected to the FET. For inverters we obtained typical high- low-level noise margins 0.4 0.3 V at bias level 1.5 V.
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