Pipelined data processing including interrupts
作者： Douglas Deao , Gary L. Swoboda , Mark R. Hammes , Nick Ing-Simmons , Keith Balmer
DOI:
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摘要: In a pipelined data processor (11), an address pipeline (39, 41) is provided to hold the addresses of instructions presently in instruction (23, 25). The facilitates tracing only executed instructions, and permits stopping during branch delay slot without losing information.
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