Data processing system with a pipelined structure for editing trace memory contents and tracing operations during system debugging

摘要: A microprocessor having a multi-stage pipeline structure, comprises: status flip-flop its output changing when the instruction code of predetermined is decoded in microprocessor; circuit for outputting synchronism with timing an address bus cycle period and sequentially storing information, which appears at input/output terminals microprocessor, as time-series data outside microprocessor. The edited by discriminating belongs to following on or before after instruction, reference information outputted from inside same.