Method and apparatus for providing deterministic read access to main memory in a computer system
作者： Nicholas Wade , Bruce Young , Mark Lalich
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摘要: A method for guaranteeing access to a bus master reads of main memory in bridge circuit joining host processor, memory, and PCI bus, by detecting read with data posted the write buffer, disabling processor selected period, presence retry access, enabling buffer after an idle passage preselected time.
lens.org 参考文章(6)
William L. Saltmarsh, Edward F. Getson, Bus access control for a multi-host system using successively decremented arbitration delay periods to allocate bus access among the hosts ,(1989)
Donald Joseph Hanrahan, Brice John Feal, David James Shippy, Least recently used arbiter with programmable high priority mode and performance monitor ,(1989)
Gary Solomon, Configuration data loopback in a bus bridge circuit ,(1993)
David A. Kummer, Robert T. Rumer, Computer system including a write protection circuit for preventing illegal write operations and a write poster with improved memory ,(1990)
David J. Foster, Armando Garcia, Robert B. Pearson, Multiprocessor system having local write cache within each data processor node ,(1991)
Montgomery C. McGraw, Paul R. Culley, John S. Thayer, Delaying arbitration of bus access in digital computers ,(1989)