作者: Chiyou Seiki , Chiyou Jiyunchin , Kou Neii , Ri Keikon
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摘要: PROBLEM TO BE SOLVED: To suppress the influence on a gate insulation film to avoid threshold voltage variation or dielectric breakdown of an MOS transistor by suppressing charge storage in polysilicon plasma etching process. SOLUTION: The is formed forming layer 610 active region 500 and contact 620 outside this connecting them through conductive material 600 wiring process, etc. A process causes having less film, than prior art, thereby reducing stored change quantity hence film.