Heterogeneous Latch-Based Asynchronous Pipelines

摘要: We present a technique to automatically synthesize heterogeneous asynchronous pipelines by combining two different latching styles: normally open D-latches for high performance and self-resetting low power. Theformer is fast but results in power consumption due data glitches that leak through the latch when it open. The latter closed opened just before stabilizes. Thus, more power-efficient slower than D-latches. propose module selection optimization assigns each pipeline stage one of these styles. This performed an automated algorithm uses types heuristics: (1) Global Critical Path (GCP), assign stages are sequentially critical, (2) estimates potential datapath glitching make SR-latch assignment decisions. has quadratic-time complexity experiments apply on several media processing kernels indicate that, average, pipelining achieves higher energy efficient either homogeneous D-latch or