2D and 3D sum-of-products array for neuromorphic computing system

摘要: An array of variable resistance cells based on a programmable threshold transistor and resistor connected in parallel is described, including 3D split gate variations. input voltage applied to the transistor, can represent variables sum-of-products operations. Programmable transistors comprise charge trapping memory transistors, such as floating or dielectric transistors. The buried implant connecting current-carrying terminals (e.g. source drain) transistor. A sensing sense amplifier configured generated by function an current cells.