Fast DES Implementation for FPGAs and Its Application to a Universal Key-Search Machine

摘要: Most modern security protocols and applications are defined to be algorithm independent, that is, they allow a choice from set of cryptographic algorithms for the same function. Although an switch is rather difficult with traditional hardware, i.e., ASIC, implementations, Field Programmable Gate Arrays (FPGAs) offer promising solution. Similarly, ASIC-based key search machine in general only applicable one specific encryption algorithm. However, key-search based on FPGAs can also independent thus wide variety ciphers. We researched feasibility universal using Data Encryption Standard (DES) as example algorithm. We designed, implemented compared various architecture options DES strong emphasis high-speed performance. Techniques like pipelining loop unrolling were used their Effectiveness investigated. The most interesting result we could achieve rates beyond 400 Mbit/s standard Xilinx FPGA. This by factor about 30 faster than software implementations while still maintaining flexibility. A cracker chip this design 6.29 million keys per second.