Delay matching for video data during expansion and compression

摘要: Video luminance data from a video signal is selectably compressed and expanded in first path including line memory. A second memory parallel processes chrominance the signal. control circuit generates respective timing signals for writing into each of memories reading memories. delay circuit, has compression expansion modes operation. During mode, delayed relative to or The duration delays can be selected range values. are out (FIFO) devices having independently enabled write read ports.