FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control

摘要: The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Metastability is achieved using precise programmable delay lines (PDL) that accurately equalize the signal arrival times PDLs are capable of adjusting propagation delays with resolutions higher than fractions pico second. In addition, real time monitoring system utilized assure high degree randomness generated output bits, resilience against fluctuations environmental conditions, as well robustness active adversarial attacks. employs feedback loop actively monitors probability bits; soon any bias observed probabilities, it adjusts through return metastable operation region. Implementation Xilinx Virtex 5 results NIST tests show effectiveness our approach.