Rapid FPGA delay characterization using clock synthesis and sparse sampling

摘要: This paper introduces a set of novel techniques for rapid post-silicon characterization FPGA timing variability. The existing built-in self-test (BIST) methods work by incrementing the clock frequency until failures occur within combinational circuit-under-test (CUT). A standing challenge industrial adoption device profiling this method is time required process. To perform and accurate delay characterization, we introduce number to rapidly scan CUTs while changing using off-chip on-chip synthesis modules. We next find compact parametric representation CUT failure probability. Using representation, minimum samples determined accurately estimate each 2D array. After that, exploit spatial correlation delays across die measure small subset from an array recover remaining entries with high accuracy. Our implementation evaluations on Xilinx Virtex 5 demonstrate that combination new reduces overhead at least three orders magnitude simultaneously reducing storage requirements.