Hardened current mode logic (cml) voter circuit, system and method
作者： David Rea , Neil Wood , Bin Li
DOI:
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摘要: A current mode logic voter circuit includes three two-input split NOR gates. Each gate receives a corresponding pair of input signals and generates first output responsive to the signals. is coupled gates receive second from The two three-input can be formed buffer circuits, in one embodiment circuits are hardened.
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