Harmonic Distortion in Switched Current Cells Due to Settling Error

摘要: An analysis of the harmonic distortion in switched-current cells produced by non-linear settling error is presented. Two approaches for computing components are addressed: discrete-time Fourier series and power expansion. They based on large signal behavior SI cell. A compact flexible expression obtained with alternative presented cases where only magnitude required. The effect charge redistribution between input sampling nodes analyzed. It shown that including effect, increased, DC gain integrator reduced. total when clock-feed-through both taken into account demonstrated minimum reached a given capacitive value. For cell designed 0.8 μm standard CMOS technology working at frequency 8 MHz, THD −72 dB can be Cgs 2.4 pF.