Process for fabricating a high density electrically programmable memory array
作者： Joseph Shappir
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摘要: A process for fabricating an MOS electrically programmable memory array which includes a plurality of floating gate devices is disclosed. The employs two layers polysilicon, each are used to define spaced-apart parallel lines with the other layer. Doped bit line regions formed in substrate alignment first prior fabrication second lines. etched gates. Overlying metal (bit lines) over doped and coupled through periodic contacts. Substantially fewer contacts required than art arrays, permitting higher density array.
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