Method to prevent bit line capacitive coupling
作者： Luan C. Tran
DOI:
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摘要: Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A cell is in triple well structure that includes substrate, the layer, an epitaxial layer. The include voltage contacts allow wells to be biased dc level. transistor which on including source drain region separated by channel region. line coupled of contact.
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