Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths

摘要: Many software compilers for embedded processors produce machine code of insufficient quality. Since most applications must meet tight speed and size constraints, is still largely developed in assembly language. In order to eliminate this bottleneck enable the use high-level language also software, new generation optimization techniques are required. This paper describes a novel technique with irregular data path architectures, such as typically found fixed-point DSPs. The proposed maps flow graph representation program into highly efficient target processor modeled by instruction set behavior. High quality ensured coupling different phases. contrast earlier works, mainly based on heuristics, our approach constraint-based. An initial constraints prescribed given model. Further arise during decisions concerning selection, register allocation, scheduling. Whenever possible, postponed until sufficient information about good decision has been collected. active "background" guarantee local satisfiability at any point time generation. mechanism permits simultaneously cope special-purpose registers level parallelism. We describe detailed integration implementation constraint logic programming (CLP) ECLiPSe. For standard DSP, we show that generated comes close hand-written code. input model can be edited user, retargetability achieved within certain class.