摘要: In this paper, we present area and performance-driven clustering techniques for coarse-grained, antifuse-based FPGAs. A macro logic cell in class of FPGAs has multiple inputs outputs. Starting with cell, a library small cells can be generated target network was mapped the library. For minimum-area clustering, our algorithm minimizes number required to cover network. Two linear equations were set up found optimal mapping solution by using equations. on critical path is minimized extension Lawler's algorithm. The results show that area-driven reduced 12.29% maximum depth 44.75% compared commercial tool.