Sequential circuit synthesis at the gate level

摘要: Sequential circuit synthesis is the process of automatically generating an optimal implementation a sequential given high-level or gate-level description. Optimization design may be performed at either state transition graph level gate level. The published work to date has favored because it allows one reason easily about input/output sequences; however, impact optimization this hard quantify. view important for several reasons: provides direct measure quality final implementation; all designs must eventually implemented level; description usually computationally impractical extract higher-level. An investigation presented herein. Two primary facets are explored: flexibility in and implementation. Flexibility implies choice function implement. exploits select that with respect some cost criterion. In dissertation, methods deriving, manipulating utilizing developed. A new model proposed handling types afforded New techniques both two-level multilevel implementations given, including formulation acyclic circuit. algorithms have been scSIS, program developed as part investigation.