Earom cell matrix and logic arrays with common memory gate

摘要: A three gate programmable memory cell comprised of a variable threshold element medial two access elements, together forming series path whose conductive state can be altered by any one the elements. Each has lines for individually accessing electrodes, in addition to line connections opposite ends formed elements series. In form, an alterable transistor is connected between field effect transistors, controlling addressing and other actuating read mode. The erased with high voltage pulse on line. Subsequent programming defined states word bit time coincidence polarity, shorter duration logic stored presence or absence through when all gates are biased their mode levels. unitary configuration includes single substrate, channel doped node regions. Electrically isolated electrodes transistors symmetrically disposed adjacent each over control its conductivity segments. cells amenable being grouped arrays, while retaining independence flexibility individual row column addresses.