Integrated circuit eeprom memory and method of programming the same

作者: Eric Scott Carman , Philippe Raguet , Erwan Hemon

DOI:

关键词:

摘要: An integrated circuit EEPROM memory array (5) of thick oxide, single poly cells (10, 20, 30, etc...) has switching circuitry on cell source electrodes (14, 24) to reduce the voltage levels that must be switched when programming (5). The (10, 20, etc...) are also provided with the drain electrodes (16, 26) block voltages. In this way the die area may be significantly reduced, resulting in reduced cost, improved reliability, and improved production yields.

参考文章(5)
Sachidanandan Sambandan, Jahanshir J. Javanifard, Sanjay S. Talreja, Duane Mills, Gate/source disturb protection for sixteen-bit flash EEPROM memory arrays ,(1992)
Murray L. Trudel, George C. Lockwood, Earom cell matrix and logic arrays with common memory gate ,(1980)
Stephen F. Sullivan, Neal R. Mielke, Flash erasable single poly EPROM device ,(1992)