Introduction to the cell multiprocessor
作者： J. A. Kahle , M. N. Day , H. P. Hofstee , C. R. Johns , T. R. Maeurer
DOI: 10.1147/RD.494.0589
关键词:
摘要: This paper provides an introductory overview of the Cell multiprocessor. represents a revolutionary extension conventional microprocessor architecture and organization. The discusses history project, program objectives challenges, disign concept, programming models, implementation.
acm.org
sci-hub.se 参考文章(11)
U. Ghoshal, R. Schmidt, Refrigeration technologies for sub-ambient temperature operation of computing systems international solid-state circuits conference. pp. 216- 217 ,(2000) , 10.1109/ISSCC.2000.839755
HS Yang, R Malik, S Narasimha, Y Li, R Divakaruni, P Agnello, S Allen, A Antreasyan, JC Arnold, K Bandy, M Belyansky, A Bonnoit, G Bronner, V Chan, X Chen, Z Chen, D Chidambarrao, A Chou, W Clark, SW Crowder, B Engel, H Harifuchi, SF Huang, R Jagannathan, FF Jamin, Y Kohyama, H Kuroda, CW Lai, HK Lee, W-H Lee, EH Lim, W Lai, A Mallikarjunan, K Matsumoto, A McKnight, J Nayak, HY Ng, S Panda, R Rengarajan, M Steigerwalt, S Subbanna, K Subramanian, J Sudijono, G Sudo, S-P Sun, B Tessier, Y Toyoshima, P Tran, R Wise, R Wong, IY Yang, CH Wann, LT Su, M Horstmann, Th Feudel, A Wei, K Frohberg, G Burbach, M Gerhardt, M Lenski, R Stephan, K Wieczorek, M Schaller, H Salz, J Hohage, H Ruelke, J Klais, P Huebler, S Luning, R Van Bentum, G Grasshoff, C Schwan, E Ehrichs, S Goad, J Buller, S Krishnan, D Greenlaw, M Raab, N Kepler, Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing international electron devices meeting. pp. 1075- 1077 ,(2004) , 10.1109/IEDM.2004.1419385
D. Pham, S. Asano, M. Bolliger, M.N. Day, H.P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Riley, D. Shippy, D. Stasiak, M. Suzuoki, M. Wang, J. Warnock, S. Weitzel, D. Wendel, T. Yamazaki, K. Yazawa, The design and implementation of a first-generation CELL processor international solid-state circuits conference. pp. 184- 592 ,(2005) , 10.1109/ISSCC.2005.1493930
Wm. A. Wulf, Sally A. McKee, Hitting the memory wall ACM SIGARCH Computer Architecture News. ,vol. 23, pp. 20- 24 ,(1995) , 10.1145/216585.216588
A. Kunimatsu, M. Oka, A. Ohba, T. Yutaka, T. Okada, M. Suzuoki, N. Ide, T. Sato, Y. Endo, H. Murakami, T. Kamei, M. Hirano, F. Ishihara, H. Tago, Vector unit architecture for emotion synthesis IEEE Micro. ,vol. 20, pp. 40- 47 ,(2000) , 10.1109/40.848471
K. Chang, S. Pamarti, K. Kaviani, E. Alon, Xudong Shi, T.J. Chin, Jie Shen, G. Yip, C. Madden, R. Schmitt, C. Yuan, F. Assaderaghi, M. Horowitz, Clocking and circuit design for a parallel I/O on a first-generation CELL processor international solid-state circuits conference. pp. 526- 615 ,(2005) , 10.1109/ISSCC.2005.1494101
R. D. Isaac, The future of CMOS technology Ibm Journal of Research and Development. ,vol. 44, pp. 369- 378 ,(2000) , 10.1147/RD.443.0369
S.H. Dhong, O. Takahashi, M. White, T. Asano, T. Nakazato, J. Silberman, A. Kawasumi, H. Yoshihara, A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor international solid-state circuits conference. pp. 486- 612 ,(2005) , 10.1109/ISSCC.2005.1494081
Philip N. Strenski, Victor Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Philip G. Emma, Pradip Bose, Optimizing pipelines for power and performance international symposium on microarchitecture. pp. 333- 344 ,(2002) , 10.5555/774861.774897
H.P. Hofstee, Power efficient processor architecture and the cell processor high-performance computer architecture. pp. 258- 262 ,(2005) , 10.1109/HPCA.2005.26