Power Analysis of an FPGA Implementation of Rijndael: Is Pipelining a DPA Countermeasure?

摘要: Since their publication in 1998, power analysis attacks have attracted significant attention within the cryptographic community. So far, they been successfully applied to different kinds of (unprotected) implementations symmetric and public-key encryption schemes. However, most published apply smart cards only a few publications assess vulnerability hardware implementations. In this paper we investigate Rijndael FPGA (Field Programmable Gate Array) attacks. The design used carry out experiments is an optimized architecture with high clock frequencies, presented at CHES 2003. First, provide clear discussion hypothesis mount attack. Then, propose theoretical predictions that confirmed experimentally, which are first successful against FPCA implementation Rijndael. addition, evaluate effect pipelining unrolling techniques terms resistance analysis. We also emphasize how efficiency attack significantly depends on knowledge design.