Efficient implementation of Rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs

摘要: Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study both hardware and software implementations. However, although plentiful papers present various implementation results, it seems that efficiency could still be greatly improved by applying good design rules adapted devices algorithms. This paper addresses approaches for efficient FPGA implementations algorithm. As different applications AES algorithm may require speed/area tradeoffs, we propose a rigorous possible schemes, but also discuss methodology algorithmic optimization in order improve previously reported results. We heuristics evaluate at steps process. define an optimal pipeline takes place route constraints into account. Resulting circuits significantly results: throughput is up 18.5 Gbits/sec area requirements can limited 542 slices 10 RAM blocks with ratio throughput/area least 25% best-known designs Xilinx Virtex-E technology.