Architectural physical synthesis
作者： William Halpin , Benoit Lemonnier , Kenneth S. McElvain
DOI:
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摘要: The present invention discloses methods and apparatuses to design an integrated circuit. According one aspect, the circuit iterative process of synthesis placement where each iteration provides incremental changes on transform is then made with accurate timing information from placement, incrementally toward final enclosure design. approach a continuous advancement vice versa, improvements knowledge current instance logic.
lens.org 参考文章(47)
Subhasis Bose, Maurice J. LeBrun, Geoffrey Mark Furnish, Methods and systems for placement ,(2007)
Chandramouli Visweswariah, Patrick M. Williams, David J. Hathaway, Jun Zhou, Method of achieving timing closure in digital integrated circuits by optimizing individual macros ,(2003)
Prabhakar Nandavar Kudva, Paul Gerard Villarrubia, Leon Stok, Andrew James Sullivan, Lakshmi Narasimha Reddy, Kanad Chakraborty, Wilm Ernst Donath, Method and apparatus for applying fine-grained transforms during placement synthesis interaction ,(2000)
Andre DeHon, Michael Wrighton, Element placement method and apparatus ,(2003)
Alexander Marquardt, Vaughn Betz, Jonathan Rose, Architecture and CAD for Deep-Submicron FPGAS ,(1999)
S.N. Adya, S. Chaturvedi, J.A. Roy, D.A. Papa, I.L. Markov, Unification of partitioning, placement and floorplanning international conference on computer aided design. pp. 550- 557 ,(2004) , 10.1109/ICCAD.2004.1382639
Adrian Dominic Thompson, Electronic circuit design World Intellectual Property Organization, Patent Cooperation Treaty. ,(2006)
Darren C. Cronquist, A system and method for reducing wire delay or congestion during synthesis of hardware solvers ,(2003)
Gregg Baeckler, Babette van Antwerpen, Yean-Yow Hwang, Michael D. Hutton, Richard Yuan, Joachim Pistorius, Physical resynthesis of a logic design ,(2003)
Hamid Savoj, Michael A. Riepe, Robert M. Swanson, Timothy M. Burks, Ginneken Lukas Van, Karen E. Vahtra, Method for generating design constraints for modulates in a hierarchical integrated circuit design system ,(2002)