High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion
作者： Greg J. Landry , Sherif Hanna , Jeyenth Vijayaraghavan , Alan ReFalo
DOI:
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摘要: Disclosed are various embodiments of a differential logic to CMOS translator including level-shifting and buffering stage configured receive inputs provide resulting signals with lower common mode voltage. Further, gain is included the increased swing signals. A buffer also output. Also disclosed method translating signal input The includes using from output
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