A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability

摘要: Various 3D NAND Flash array architectures including P-BiCS, TCAT, VSAT, and VG are critically examined in this work by extensive TCAD simulations. All structures have X,Y lateral scaling limitation since the minimal ONO thickness (∼20 nm) poly channel (∼10nm) can not be scaled further. Among them may best X-direction scalability to F∼2X nm node, no penalty of increasing Z layer number current flows horizontally. We propose a buried-channel junction-free improve read for all arrays our simulation results well support structure. For first time, “Z-interference” is it indicates new Z-direction limitation. The present crucial importance understanding various approaches.