3D Non-Volatile Memory With Metal Silicide Interconnect

摘要: A stacked non-volatile memory cell array include areas with rows of vertical columns NAND cells, and an interconnect area, e.g., midway in the extending a length array. The area includes at least one metal silicide between insulation-filled slits, does not cells. can route power control signals from below stack to above stack. also be formed peripheral region substrate. Contact structures extend terraced portion upper layer, stack, complete conductive path circuitry layer. Subarrays provided plane without word line hook-up transfer subarrays.