作者: S. Pingel , O. Frank , M. Winkler , S. Daryan , T. Geipel
DOI: 10.1109/PVSC.2010.5616823
关键词:
摘要: Since solar energy generation is getting more and important worldwide PV systems parks are becoming larger consisting of an increasing number panels being serially interconnected. As a consequence frequently exposed to high relative potentials towards ground causing High Voltage Stress (HVS). The effect HVS on long term stability depending the leakage current between cells has been first addressed by NREL in 2005 [1]. This potential degradation mechanism not monitored typical tests listed IEC 61215 [2]. Depending technology different types Potential Induced Degradation (PID) occur. paper focusing PID wafer based standard p-type silicon aiming life times for once external field. A test setup presented simulation lab influence cell properties demonstrated order reveal precondition PID. However, can also be stopped or minimized panel system level as shown paper.