Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features
作者： Frank Worrell , Keith D. Au
DOI:
关键词:
摘要: An arbitration logic including one or more modular priority encoders. Each encoder includes a first circuit, comparator second and an circuit. The circuit may be configured to generate output signal in response plurality of request signals. compare all possible pairs control (i) the signals (ii) result comparing signal.
google.ch 参考文章(45)
Jeffrey Kuskin, Gregory Chesson, Flexible scheduling architecture ,(2003)
Steven C. Miller, High bandwidth PCI to packet switched router bridge having minimized memory latency ,(1997)
Paul von Stamwitz, Byron Arlen Young, Method of operation of a host adapter integrated circuit ,(1995)
Christopher Bloxham, Kathryn E. Rickard, Direct memory access controller and method of filtering data during data transfer from a source memory to a destination memory ,(2002)
Chang-Ming Lin, Data alignment systems and methods ,(2003)
Franck Seigneret, Praveen Kolli, Sivayya Ayinala, Prabha Atluri, Nabil Khalifa, Multi-threaded DMA ,(2004)
Andrew Mark Nightingale, Testing compliance of a device with a bus protocol ,(2002)
Matt E. Buckelew, James L. Deming, Mark A. Mosley, Steven J. Heinrich, Clifford A. Whitmore, Stewart G. Carlton, Michael S. Farmer, High-speed video frame buffer using single port memory chips ,(1997)