Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

摘要: This paper proposes a novel sub-architecture to optimize the data flow of REMUS-II (REconfigurable MUltimedia System 2), dynamically coarse grain reconfigurable architecture. consists µPU (Micro-Processor Unit) and two RPUs (Reconfigurable Processor Unit), which are used speeds up control-intensive tasks data-intensive respectively. The parallel computing capability flexibility makes itself an excellent candidate process multimedia applications, require large amount memory accesses. In this paper, we specifically deal with those performance-hazard energy-hungry accessing in order meet bandwidth requirement computing. RPU internal could work multiple modes, like 2D-access mode transformation mode, according different access patterns. design can improve performance 26% compared traditional on-chip memory. Meanwhile, block buffer is implemented off-chip through reducing accesses, 43% direct DDR access. Based on RTL simulation, achieve 1080p@30fps H.264 High Profile@ Level 4 MPEG2 at 200MHz clock frequency. into 23.7mm2 silicon TSMC 65nm logic 400MHz maximum working