Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture

摘要: Using the coarser operand grain and simplified interconnection patterns, CGRA (coarse grained reconfigurable architectures) has been proven to be energy efficient in several specific domains. As we know, speed at which contexts are applied a PEA (processing element array) directly determines performance of CGRA. In this paper, design space is further developed from configuration granularity perspective by one middle-grained granularity—the row-based mechanism (RCM). The most prominent feature RCM that large DFG (data flow graph) can mapped onto small array once reconfiguration, carried out on row-by-row basis. Compared with an ordinary DFG-partitioning solution, reconfiguration time data transfer well reduced. Furthermore, proposed offers much more storage for contexts. partitioning boosted 2.6% 57.8%, while area penalty only 4.79% power 7.22%. used processor called REMUS HPA (reconfigurable multi-media system, high version advanced). implemented 50.5 mm2 silicon TSMC 65 nm technology. Simulation shows 1920×1088@37 fps achieved H.264 high-profile decoding when exploiting 200 MHz working frequency. XPP (one commercial processor), 247% boosted.