作者: Ning Wu , Xiaoqiang Zhang , Yunfei Ye , Lidong Lan
DOI: 10.1007/978-94-017-9115-1_11
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摘要: In this work, a new multi-term common subexpression elimination (CSE) algorithm is proposed. The aims to reduce area-delay-production (ADP) in VLSI designs of constant matrix multiplication (CMM) over binary field. For promoting delays optimization, gate-level delay computing method used compute the based on transformed matrices. also takes greedy search minimal ADP result. worst case computational complexities and CSE are analyzed, respectively. Experimental results have shown that has more efficient reduction CMM.