Analysis of an SOC Architecture for MPEG Reconfigurable Video Coding Framework

作者: Jer-Min Hsiao , Chun-Jen Tsai

DOI: 10.1109/ISCAS.2007.377997

关键词:

摘要: Due to the variety of popular video coding standards, many efforts have been put into design a single decoder chip that supports multiple formats. In 2004, ISO/IEC MPEG started new work item facilitate multi-format codec and enable more flexible usage tools. The has turned reconfigurable (RVC) framework. key concept RVC framework is allow reconfiguration tools create different solutions on-the-fly. this paper, SoC architecture proposed support Some analysis conducted show extra costs required for platform compared hard-wired architecture. conclusion, can be mapped an provide flexibility scalability dynamic application environment with reasonable cost in hardware design.

参考文章(1)
Tung-Chien Chen, Yu-Wen Huang, Liang-Gee Chen, Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture international symposium on circuits and systems. ,vol. 2, pp. 273- 276 ,(2004) , 10.1109/ISCAS.2004.1329261