Compressing scenarios of electronic circuits
作者： Chaeryung Park , Mayank Shrivastava
DOI:
关键词:
摘要: The number of scenarios analyzed for an electronic circuit is reduced to improve the processing time and resource requirements design automation processes. Each scenario associated with a mode corner circuit. Groups corresponding different corners same are identified. A winner from each group identified, example, by selecting dominant that covers most violations in group. adjusted account other adjustment violation timing node another performed reducing required margin. margin determined based on information scaled differences between two scenarios.
lens.org 参考文章(3)
Feroze P. Taraporevala, Marina Ovchinnikov, Amit Goel, Kayhan Kucukcakar, Praveen Ghanta, Jinfeng Liu, Simultaneous multi-corner static timing analysis using samples-based static timing infrastructure ,(2011)
John P. Dubuque, Chandramouli Visweswariah, Kerim Kalafala, Eric A. Foreman, Nathan C. Buck, Gregory M. Schaeffer, Peter A. Habitz, Timing closure using multiple timing runs which distribute the frequency of identified fails per timing corner ,(2008)
Loa Mize, Qiuyang Wu, Kayhan Küçükçakar, Brian Clerkin, Steve Hollands, Andrew J. Seigel, Subramanyam Sripada, System and method for providing distributed static timing analysis with merged results ,(2004)