Command-based control of NAND flash memory
作者： Sean S. Eilert , Shekoufeh Qawami , Rodney R. Rozman
DOI:
关键词:
摘要: Some embodiments of the invention use a command-based interface to control reads and writes with non-volatile memory devices. This may reduce number pins that are needed on each integrated circuit, therefore cost size those circuits. In some embodiments, an on-die cache buffer be used data transfers between high-speed bus slower speed array.
lens.org参考文章(13)
Michel E. Gannage, Nagesh Challa, Solid state memory device having serial input/output ,(1993)
David Eggleston, Kevin Kilbuck, Non-volatile memory with synchronous DRAM interface ,(2004)
Kwan-Weon Kim, Synchronous memory device with reduced address pins ,(2002)
Hideaki Kurata, Shunichi Saeki, Naoki Kobayashi, Non-volatile semiconductor memory device and semiconductor disk device ,(2004)
Earl T. Cohen, Ricardo H. Bruce, Rolando H. Bruce, Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers ,(1997)
Henry Stracovsky, Brent Keeth, Desi Rhoden, Kevin J. Ryan, Yoshikazu Morooka, Jean Crepeau, Cormac M. O'Connell, Donald N. North, Troy A. Manning, Bruce Millar, David B. Gustavson, Terry R. Lee, Peter B. Gillingham, David V. James, Hans A. Wiggers, Memory system having synchronous-link DRAM (SLDRAM) devices and controller ,(1998)
Christophe Chevallier, Vinod Lakhani, Robert Norman, Memory system having flexible addressing and method ,(2001)
Ronald T. Taylor, Michael E. Runas, Sudhir Sharma, Memory system with multiplexed input-output port and memory mapping capability ,(1996)
Yoshikazu Shibata, Data transfer system having a channel adapter with varying data transfer lengths ,(1988)