Continuous read burst support at high clock rates
作者： Clifford Alan Zitlaw
DOI:
关键词:
摘要: A memory device includes a array, an output buffer, initial latency register, and signal. Often times host that interfaces with the is clocked at high rate such data extraction rates of are not adequate to support gapless transfer. The signal operable stall transmission between when from array buffer.
lens.org 参考文章(11)
Richard V. De Caro, Danut I Manea, Method and system to access memory ,(2008)
Michael J. Miller, Michael J. Morrison, Jay B. Patel, Philip A. Ferolito, Reducing latency in serializer-deserializer links ,(2012)
Hyun Lee, Jayesh R. Bhakta, System and method utilizing distributed byte-wise buffers on a memory module ,(2010)
David Q. Chow, Ming-Shiang Shen, Abraham Chih-Kang Ma, Charles C. Lee, I-Kang Yu, High Performance and Endurance Non-volatile Memory Based Storage Systems ,(2008)
George Wayne Nation, Gurumani Senthil, Gary Scott Delp, Methods and structures for improved buffer management and dynamic adaption of flow control status in high-speed communication networks ,(2002)
Atif Sarwari, Methods of fabricating integrated imager and microcontroller ,(2009)
Chaofeng Huang, Shahram Abdollahi-Alibeik, Delay line and output clock generator using same ,(2003)
Sean S. Eilert, Shekoufeh Qawami, Rodney R. Rozman, Command-based control of NAND flash memory ,(2006)
Choi Young-Joon, Cho Hyun-Duk, Kim Tae-Kyun, OneNAND FLASH MEMORY AND DATA PROCESSING SYSTEM INCLUDING THE SAME ,(2006)
Koji Shimbayashi, Storing apparatus and method for controlling the same ,(2005)