CMOS and Bipolar Technologies

作者: Vadim Issakov , Vadim Issakov

DOI: 10.1007/978-3-642-13598-9_3

关键词:

摘要: Performance capability of circuits depends to a great extent on the available semiconductor technology. Numerous parameters related device, metallization or substrate properties circumscribe achievable circuit characteristics at microwave frequencies and thus can be used for technology comparison.

参考文章(17)
Trond Ytterdal, Tor A. Fjeldly, Yuhua Cheng, Device Modeling for Analog and RF CMOS Circuit Design ,(2003)
J. Bock, H. Schiffer, K. Auflnger, R. Stengl, S. Boguth, R. Schreiter, M. Rest, R. Knapp, M. Wurzer, W. Pemdl, T. Bottner, T.F. Meister, SiGe bipolar technology for automotive radar applications bipolar/bicmos circuits and technology meeting. pp. 84- 87 ,(2004) , 10.1109/BIPOL.2004.1365751
K. Aufinger, K. Beock, R. Gabl, T.F. Meister, Low-Frequency Noise Characteristics of Advanced Si and SiGe Bipolar Transistors european solid-state device research conference. pp. 536- 539 ,(1997) , 10.1109/ESSDERC.1997.194484
R. Vytla, T. Meister, K. Aufinger, D. Lukashevich, S. Boguth, H. Knapp, J. Bock, H. Schafer, R. Lachner, Simultaneous Integration of SiGe High Speed Transistors and High Voltage Transistors bipolar/bicmos circuits and technology meeting. pp. 1- 4 ,(2006) , 10.1109/BIPOL.2006.311159
M. Tiebout, Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS IEEE Journal of Solid-state Circuits. ,vol. 36, pp. 1018- 1024 ,(2001) , 10.1109/4.933456
H. K. Gummel, H. C. Poon, An Integral Charge Control Model of Bipolar Transistors Bell System Technical Journal. ,vol. 49, pp. 827- 852 ,(1970) , 10.1002/J.1538-7305.1970.TB01803.X
M.J. Deen, C.-H. Chen, S. Asgaran, G.A. Rezvani, J. Tao, Y. Kiyota, High-Frequency Noise of Modern MOSFETs: Compact Modeling and Measurement Issues IEEE Transactions on Electron Devices. ,vol. 53, pp. 2062- 2081 ,(2006) , 10.1109/TED.2006.880370
T. Schiml, S. Biesemans, G. Brase, L. Burrell, A. Cowley, K.C. Chen, A. Von Ehrenwall, B. Von Ehrenwall, P. Felsner, J. Gill, F. Grellner, F. Guarin, L.K. Han, M. Hoinkis, E. Hsiung, E. Kaltalioglu, P. Kim, G. Knoblinger, S. Kulkarni, A. Leslie, T. Mono, T. Schafbauer, U. Schroeder, K. Schruefer, T. Spooner, D. Warner, C. Wang, R. Wong, E. Demm, P. Leung, A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications symposium on vlsi technology. pp. 101- 102 ,(2001) , 10.1109/VLSIT.2001.934969