RTL modeling and simulation using JAVA
作者： Eric Ohana , Cristina Luca
DOI: 10.1109/OPTIM.2012.6231833
关键词:
摘要: This paper presents a JAVA based framework for RTL modeling and simulation of digital hardware designs. After linking between object-oriented concepts models, the analogy to features found in widely used description language like Verilog is laid down. While focusing primarily on synchronous designs cycle simulation, way broaden this scope event driven pointed out. Using general programming paves more seamless software integration typical system.
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