Reduced latency IEEE floating-point standard adder architectures

摘要: The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the significand addition. implemented in 0.5 /spl mu/m CMOS, measures 1.8 mm/sup 2/, has 3-cycle latency implements all modes. A modified version this can perform accumulation 2-cycles small amount extra hardware for use parallel processor node. This achieved by feeding back previous un-normalised but correctly rounded result together normalisation distance. 2-cycle architecture potentially same cycle time that also employs flagged addition described. It incorporates fast prediction scheme true subtraction significands an exponent difference 1, one less adder.