Forward Error Correction for 64b66b Coded Systems
作者： Frank J. Effenberger
DOI:
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摘要: A network component comprising a processor configured to implement method that comprises applying forward error correction (FEC) algorithm plurality of data blocks generate redundancy data, encapsulating an integer number the and in FEC codeword, transmitting wherein codeword is about evenly aligned with transmission clock time quanta have rate. selecting generates from blocks, EEC encapsulates synchronization pattern add such codewords are quanta.
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