Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates

摘要: An interface circuit permits a first bus master connected to directly access main memory second while maintaining coherency between corresponding data in the and cache used by on bus. The maps selected addresses such that when attempts read or write one of mapped addresses, responds accessing address stores SNOOP indicating which contain cached memory, address, places signal telling copy from into before performs after completes access, thereby maintain memory.