Structure and method for an asynchronous communication protocol between master and slave processors

摘要: In accordance with the present invention, a structure and method for asynchronously interfacing master processor slave is provided by receiving from providing to device control signals of polling protocol, an interrupt type protocol. first embodiment this provides WR (write request), RD (read OE (output enable) signals, receives BUSY (busy) signal. The "int" (interrupt) signal, "intack" (interrupt acknowledge), "outs" (output), "ins" (input) signals. second instead signal embodiment, read request AND product AS (address strobe) most significant bit address.