Estimating capacitance effects in integrated circuits using congestion estimations
作者： Chih-liang Cheng
DOI:
关键词:
摘要: A method estimates the capacitance effects of an interconnect prior to routing integrated circuit (IC) design, as follows. The design is divided into areas. Capacitance for each area are estimated based on congestion ratios within area. derived from estimations demand resources in net net-list included IC design. Coupling vectors ratios. then by looking up a database using coupling vectors. resulting per-area used estimate traversing total due multiple areas determined applying dimensions portions
google.com.mx 参考文章(11)
Saila Ponnapalli, Timothy Lehner, Sanjay Upreti, Method of extracting 3-D capacitance and inductance parasitics in sub-micron VLSI chip designs using pattern recognition and parameterization ,(1998)
Paul Gerard Villarrubia, Alan Charles Folta, Parsotam Trikam Patel, Sharad Mehrotra, Method and system for characterizing interconnect data within an integrated circuit for facilitating parasitic capacitance estimation ,(1996)
Chung-Kuan Cheng, So-Zen Yao, Interconnect delay driven placement and routing of an integrated circuit design ,(2000)
Gabriel Robins, Alexander Zelikovsky, Improved Steiner tree approximation in graphs symposium on discrete algorithms. pp. 770- 779 ,(2000) , 10.5555/338219.338638
Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden, Performance optimization of VLSI interconnect layout Integration. ,vol. 21, pp. 1- 94 ,(1996) , 10.1016/S0167-9260(96)00008-9
Joseph L Ganley, Computing optimal rectilinear Steiner trees: a survey and experimental evaluation Discrete Applied Mathematics. ,vol. 90, pp. 161- 171 ,(1999) , 10.1016/S0166-218X(98)00089-4
Deborah Chao Wang, Method for estimating routability and congestion in a cell placement for integrated circuit chip ,(1994)
V.V. Vazirani, I.I. Mandoiu, J.L. Ganley, A new heuristic for rectilinear Steiner trees international conference on computer aided design. ,vol. 19, pp. 157- 162 ,(1999) , 10.5555/339492.339612
Chih-liang Eric Cheng, Method for automatic iterative area placement of module cells in an integrated circuit layout ,(1996)
Parsotam Trikam Patel, Sharad Mehrotra, Method and system for performing capacitance estimations on an integrated circuit design routed by a global routing tool ,(1999)