Transactional execution processor having a co-processor accelerator, both sharing a higher level cache

作者: Fadi Y. Busaba , Eric M. Schwarz , Michael Karl Gschwind , Chung-Lung K. Shum

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摘要: A higher level shared cache of a hierarchical multi-processor system utilizes transaction identifiers to manage memory conflicts in corresponding transactions. The is with two or more processors. processor may have accelerator that performs operations on behalf the processor. Transaction indicators are set lines being accessed. aborts if conflict transaction's from another detected, and invalidated. For successfully completing transaction, committed data store stored.

参考文章(69)
Yasuko Eckert, Lisa R. Hsu, Kai K. Chang, Gabriel H. Loh, Management of caches ,(2013)
Eric Fromm, Transactional memory proxy ,(2013)
James Alan Vonderheide, Nicola Stiff, Peter Ciurea, Laura Digioacchino, Leigh Amaro, Systems and Methods to Configure Data for Diverse Services ,(2012)
Tatiana Shpeisman, Ali-Reza Adl-Tabatabai, Vijay Menon, Bratin Saha, Efficient non-transactional write barriers for strong atomicity ,(2011)
Michael P. Hohmuth, Stephan Diestelhorst, Martin T. Pohlack, David S. Christie, Jaewoong Chung, Protecting large objects within an advanced synchronization facility ,(2011)
Quinn A. Jacobson, Maurice P. Herlihy, Marc Tremblay, Shailender Chaudhry, Mark S. Moir, Selectively unmarking load-marked cache lines during transactional program execution ,(2006)
Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Bret L. Toll, Martin G. Dixon, Method, apparatus, and system for transactional speculation control instructions ,(2012)