作者: Fadi Y. Busaba , Eric M. Schwarz , Michael Karl Gschwind , Chung-Lung K. Shum
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摘要: A higher level shared cache of a hierarchical multi-processor system utilizes transaction identifiers to manage memory conflicts in corresponding transactions. The is with two or more processors. processor may have accelerator that performs operations on behalf the processor. Transaction indicators are set lines being accessed. aborts if conflict transaction's from another detected, and invalidated. For successfully completing transaction, committed data store stored.