摘要: This paper provides an overview of algorithmic noise-tolerance (ANT) for designing reliable and energy-efficient digital signal processing systems. Techniques such as prediction-based, error cancellation-based, reduced precision redundancy based ANT are discussed. Average energy-savings range from 67% to 71% over conventional Fluid IP core generators proposed a means encapsulating the benefits ANT-based low-power design methodology. CAD issues resident in methodology also
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Jan M. Rabaey, Massoud Pedram, Power Aware Design Methodologies ,(2002)
Byonghyo Shim, N.R. Shanbhag, Reduced precision redundancy for low-power digital filtering asilomar conference on signals, systems and computers. ,vol. 1, pp. 148- 152 ,(2001) , 10.1109/ACSSC.2001.986896
J.D. Meindl, J.A. Davis, The fundamental limit on binary switching energy for terascale integration (TSI) IEEE Journal of Solid-state Circuits. ,vol. 35, pp. 1515- 1516 ,(2000) , 10.1109/4.871332
Naresh Shanbhag, K. Soumyanath, Samuel Martin, Reliable low-power design in the presence of deep submicron noise (embedded tutorial session) Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00. pp. 295- 302 ,(2000) , 10.1145/344166.344642
B. Hajek, T. Weller, On the maximum tolerable noise for reliable computation by formulas IEEE Transactions on Information Theory. ,vol. 37, pp. 388- 391 ,(1991) , 10.1109/18.75261
P. Abshire, A.G. Andreou, Capacity and energy cost of information in biological and silicon photoreceptors Proceedings of the IEEE. ,vol. 89, pp. 1052- 1064 ,(2001) , 10.1109/5.939817
N.R. Shanbhag, A mathematical basis for power-reduction in digital VLSI systems IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing. ,vol. 44, pp. 935- 951 ,(1997) , 10.1109/82.644047
A.P. Chandrakasan, R.W. Brodersen, Minimizing power consumption in digital CMOS circuits Proceedings of the IEEE. ,vol. 83, pp. 498- 523 ,(1995) , 10.1109/5.371964
P.P. Sotiriadis, A. Chandrakasan, V. Tarokh, Maximum achievable energy reduction using coding with applications to deep sub-micron buses international symposium on circuits and systems. ,vol. 1, pp. 85- 88 ,(2002) , 10.1109/ISCAS.2002.1009783
R. Hegde, N.R. Shanbhag, Soft digital signal processing IEEE Transactions on Very Large Scale Integration Systems. ,vol. 9, pp. 813- 823 ,(2001) , 10.1109/92.974895