Low Power Trellis Decoder with Overscaled Supply Voltage

摘要: This paper is interested in applying voltage over-scaling (VOS) to reduce trellis decoder energy consumption, where the key issue how minimize decoding performance degradation due VOS-induced errors. Based on fact that integrity of different bits state metric has (largely) effect overall performance, we proposed an importance-aware clock skew scheduling technique assigns those more important with longer timing slacks and hence better immunity will provide system-level tolerance errors decoders. With Viterbi Max-Log-MAP decoders as test vehicles, demonstrated about 30% savings computation can be realized negligible degradation.