Special session 12B: Embedded tutorial test and fault tolerance of networks-on-chip

摘要: This embedded tutorial presents an overview of the issues related to test, diagnosis and fault-tolerance Networks-on-chip (NoCs). The main motivation is increasing interest on NoC-based designs in academia industry. new design option becoming important trend because its advantages tackling challenges a complex SoC design. However, become real standard or industrial reality, it that testing are also well understood dominated. Initially, test diagnose faults NoCs presented. A NoC basically made up three components: network interface, routers communication channels. To start with interface routers, many works presented problem suggesting wide variety DfT solutions can be used. deeper evaluation approaches brought from board-level chip-level testing, shows much better results, terms silicon overhead, time diagnosability, obtained if specific for Testing channels important. huge number interconnects allied shrinking chip dimensions make prone growing interconnect faults. capability detecting SoCs mandatory yield improvement. Moreover, fault links help tolerance mitigate maintain service. most influent strategies comparatively discussed this tutorial. In fact, correctness on-chip behavior feature must ensured, not only mode, but during mission system. all system implemented through designers assume certain Quality Service (QoS) level according techniques. current technologies quite sensitive noise cosmic particles cause transient Thus, ensure service compromised by those way, techniques infrastructure considered when designing Various detect recover permanent For last years have been proposed NoCs. Although relatively topic, research covers already considerable spectrum analysis at point summarize scientific technological advances so far identify open still need tackled.