Low power, no deadzone phase frequency detector with charge pump

作者: Matthias Locher

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摘要: In a frequency synthesizer with phase locked loop charge pump (2) is present an idle path (5-C, 6-C, 7, 8). The 8) activated only shortly before up or down pulse appears at output (15, 16) of detector (1) and the disabled after disappearance signal. Means (20) to generate signal for controlling enablement disablement may comprise down-counter divider (30) zipper (35).

参考文章(5)
Jeffrey K. Greason, Ian Young, Keng L. Wong, PLL clock generator integrated with microprocessor ,(1992)
M.G. Johnson, E.L. Hudson, A variable delay line PLL for CPU-coprocessor synchronization IEEE Journal of Solid-state Circuits. ,vol. 23, pp. 1218- 1223 ,(1988) , 10.1109/4.5947
C. Vaucher, D. Kasperkovitz, A wide-band tuning system for fully integrated satellite receivers IEEE Journal of Solid-state Circuits. ,vol. 33, pp. 987- 997 ,(1998) , 10.1109/4.701238