System for adjusting a power supply level of a digital processing component and method of operating the same
作者： Dragan Maksimovic , Sandeep Dhar
DOI:
关键词:
摘要: There is disclosed control circuitry (125) for adjusting a power supply level, VDD, of digital processing component (100) having varying operating frequencies. The comprises N delay cells (201) and adjustment (210, 215, 220). are coupled in series, each which has D determined by value such that clock edge applied to an input first cell (201a) ripples sequentially through the (201n). 220) capable VDD operable (i) monitor outputs at least K K+1 (201), (ii) determine reached output not (iii) generate signal response thereto.
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