Phase latched differential charge pump circuit and method

作者: David Edward Jefferson

DOI:

关键词: Record lockingControl theoryLoop (topology)Phase (waves)PhysicsFilter (video)Delay-locked loopCharge (physics)Phase-locked loopCharge pump

摘要: A loop circuit such as a delay lock or phase includes circuitry for changing the strength of after has been achieved. Before is achieved, charge pump that controls in low-pass filter may be relatively weak. After increased so can maintain its locked condition noisy environment.

参考文章(7)
Richard A. Erhart, Barry W. Herold, Omid Tahernia, Adaptive lock time controller for a frequency synthesizer and method therefor ,(1991)
Bahram Ahanin, Francis B. Heile, Richard G. Cliff, Kerry Veenstra, Bruce B. Pedersen, Craig S. Lytle, Programmable logic array having local and long distance conductors ,(1992)
A. Waizman, A delay line loop for frequency synthesis of de-skewed clock international solid-state circuits conference. pp. 298- 299 ,(1994) , 10.1109/ISSCC.1994.344633
U. Ko, S.A. Wichman, S. Castrianni, A 30-ps jitter, 3.6-/spl mu/s locking, 3.3-volt digital PLL for CMOS gate arrays custom integrated circuits conference. ,(1993) , 10.1109/CICC.1993.590756
Robert F. Hartmann, Hock-Chuen So, Stanley John Kopec, Sau-Ching Wong, Programmable logic device with array blocks connected via a programmable interconnect array ,(1989)
A. Efendovich, Y. Afek, C. Sella, Z. Bikowsky, Multifrequency zero-jitter delay-locked loop IEEE Journal of Solid-state Circuits. ,vol. 29, pp. 67- 70 ,(1994) , 10.1109/4.272097
Mark E. Fitzpatrick, Andrew C. Graham, Robert C. Burd, Logic array having high frequency internal clocking ,(1992)